The present invention relates to a semiconductor integrated circuit device (hereinafter called LSI device) and a method of testing the same. More particularly, the present invention relates to LSI devices and a method of testing the same, capable of detecting faults of an LSI device at high speed and with high precision without lowering the performance of an LSI device.
A conventional method of detecting a faulty gate in an LSI device is disclosed in, for example, Proceedings of the IEEE, Vol. 71, No. 1, pp. 98 to 112, January 1983. The outline of this testing method will be described with reference to FIG. 2. The term "fault" used in the above-noted Proceedings means that a signal level is fixed to (stuck at) a certain level An LSI device 1 is constructed of a plurality of gates 2. A test pattern 4 composed of "1" and "0" as shown in FIG. 2 is applied to a number of signal input pins 3 to obtain output data 5 from a number of signal output pins 6. If the output data 5 are different from the expected fault-free machine's output data, the output data 5 are compared with a fault simulation table to thereby detect a fault, in this example, a No. 3 faulty gate 7. The fault simulation table has the contents as shown in FIG. 2. With this table, the number C of a faulty gate can be identified based on the test pattern A and the corresponding output data B. Such tables are prepared for each type of LSI devices and used when LSI devices are tested. In the table shown in FIG. 2, the item No. 4 indicates that the gate No. 3 is a faulty gate. The test pattern A=1010110 and the output data B=0011010 correspond to the item No. 4 which indicates that the gate No. 3 is a faulty gate. The fault mode D shows the contents of a fault. For example, at the item No. 4, the output of the No. 3 gate is stuck at "0" level.
The above conventional technique has the following three problems.
(1) Sets of the same test patterns and output data are present so that a faulty gate cannot be correctly identified.
(2) The capacity of a fault simulation table becomes drastically large if a plurality of faulty gates are intended to be detected at a time. It is therefore difficult to form such a table. It is possible to use a faulty simulation table intended to detect faults one at a time. However, it takes a long time to detect all the faults if this approach is followed. Moreover, a problem exists that, in certain instances, a plurality of faults are cancelled out each other and it seems that there is no fault.
(3) It is necessary to prepare a fault simulation table for each type of LSI devices This work increases the time and cost required for the development of LSI devices.
The above three problems will be described more detail.